The netlist output by synthesis doesn’t include the IP logic, which is added during place and route. Synthesis does not change the IP, whose netlist is used for timing and resource estimation. In a white-box methodology for gate-level IP, the IP netlist is added as a read-only model. The netlist output by synthesis includes the IP logic, so there is no need to provide the IP separately to the place and route process. In an Absorb methodology, the IP logic can be optimized as part of the larger design during synthesis. There are various ways in which IP can be incorporated in a design: by being absorbed into the design’s RTL, or incorporated as a white box, grey box or black box model.
user requirements, such as QoR, visibility, and stability.the content type: RTL, netlist or synthesis models.The flow you use to manage your IP will depend on a number of factors:
#How to use synplify pro generator#
Tools such as Synopsys’ Synplify can ingest all the IP files created by an IP vendor’s generator tool and use them as input to its integration process. An IP packaging tool is necessary so that end users can generate the specific version of the IP they need, target it to their choice of FPGA, and get a licensed file for integration. More complex distribution strategies are necessary if creators are distributing configurable IP, targeting specific implementation technologies, or for licensing reasons. In the simplest IP creation process, a team develops an IP block, compresses the file and sends it to the design team, which unpacks it and integrates the RTL into the top level of its design, which is then synthesized and implemented as a whole.Ī slightly more complex approach sees the creation team including constraints with the RTL, which are then used to inform the place and route process. Optimised approaches to managing and using third-party IP, and packaging your own IP for reuse, can help ensure that methodology issues don’t undermine the advantages of using IP in FPGA-based designs. The combination of FPGAs and IP blocks enables teams to develop and try out complex designs quickly. How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices
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